The present invention described herein relates to an oscillator and a method for operating the same.
Typically, oscillators are used to provide a clock signal or a timing signal to electronic circuits such as microprocessors, micro-controllers, flip-flops, and latches, and are used widely in electronic systems. An accurate and stable reference frequency can be obtained using a crystal oscillator.
However, since many application fields do not require such a high-quality reference frequency and are subject to the requirements of mass production, a resistor-capacitor oscillator is used as a lower-cost source of a clock signal source or a timing signal. The resistor-capacitor oscillator is advantageous in that it generates a variable frequency by changing a resistance R or a capacitance C and also makes it possible to avoid the use of an inductor that is difficult to fabricate in an integrated circuit.
Low power consumption is desirable in mobile systems that use a battery, such as mobile communication devices and portable electronic devices. Low power consumption is advantageous in increasing the lifetime of the battery. Thus, in such application fields, it is generally advantageous to use an ultralow-power resistor-capacitor oscillator that is low in power consumption.
FIG. 1 is a circuit diagram of a typical resistor-capacitor oscillator.
Referring to FIG. 1, a resistor-capacitor oscillator 1 includes a reference voltage generator circuit 10, a voltage comparator circuit 20, an oscillation signal generator circuit 30, a frequency voltage generator circuit 40, and an output circuit 50. The reference voltage generator circuit 10 generates a first reference voltage V1 and a second reference voltage V2 by resistance division. The voltage comparator circuit 20 includes a first comparator circuit 22 comparing the first reference voltage V1 with a frequency voltage Vf, and a second comparator circuit 24 comparing the second reference voltage V2 with the frequency voltage Vf.
FIG. 2 is a timing diagram illustrating an oscillation clock generated by the resistor-capacitor oscillator 1 illustrated in FIG. 1.
Referring to FIGS. 1 and 2, an oscillation clock OSCK is generated as follows. The voltage level of an oscillation signal OS is low at an initial condition. Thus, in the frequency voltage generator circuit 40, a PMOS transistor PM is turned on and an NMOS transistor NM is turned off. Thus, a capacitor 44 starts to be charged. Accordingly, the frequency voltage Vf increases depending on a time constant RfCf. In general, the frequency voltage Vf increases according to Equation (1).
                              V          f                =                              (                          1              -                              ⅇ                                  -                                      t                                                                  R                        f                                            ⁢                                              C                        f                                                                                                                  )                    ⁢          VDD                                    (        1        )            
The first comparator circuit 22 compares the first reference voltage V1 with the frequency voltage Vf, and outputs a set pulse Vs when the first reference voltage V1 is equal to the frequency voltage Vf. Herein, the first reference voltage V1 satisfies Equation (2) according to voltage division.
                              V          1                =                                            n              +              1                                      n              +              2                                ⁢          VDD                                    (        2        )            
For generation of the set pulse Vs, the first reference voltage V1 must be equal to the frequency voltage Vf. Therefore, Equation (3) is derived from Equation (1) and Equation (2).
                              1          -                      ⅇ                          -                              t                                                      R                    f                                    ⁢                                      C                    f                                                                                      =                              n            +            1                                n            +            2                                              (        3        )            
The oscillation signal generator circuit 30 latches a high level in response to the set pulse Vs. Thus, the oscillation clock OSCK will maintain a high-level state for a predetermined period. In contrast, if the oscillation signal OS is at a high level, the PMOS transistor PM of the frequency voltage generator circuit 40 is turned off and the NMOS transistor NM is turned on. Thus, the capacitor 44 starts to be discharged to ground GND. Accordingly, the frequency voltage Vf decreases depending on the time constant RfCf. In general, the frequency voltage Vf decreases according to Equation (4).
                              V          f                =                              ⅇ                          -                              t                                                      R                    f                                    ⁢                                      C                    f                                                                                ⁢          VDD                                    (        4        )            
The second comparator circuit 24 compares the second reference voltage V2 with the frequency voltage Vf, and outputs a reset pulse Vr when the second reference voltage V2 is equal to the frequency voltage Vf. Herein, the second reference voltage V2 satisfies Equation (5) according to voltage division.
                              V          2                =                              1                          n              +              2                                ⁢          VDD                                    (        5        )            
For generation of the reset pulse Vr, the second reference voltage V2 must be equal to the frequency voltage Vf. Therefore, Equation (6) is derived from Equation (4) and Equation (5).
                              ⅇ                      -                          t                                                R                  f                                ⁢                                  C                  f                                                                    =                  1                      n            +            2                                              (        6        )            
The oscillation signal generator circuit 30 latches a low level in response to the reset pulse Vr. Thus, the oscillation clock OSCK will maintain a high-level state for a predetermined period. In contrast, if the oscillation signal OS is at a low level, the PMOS transistor PM of the frequency voltage generator circuit 40 is turned on and the NMOS transistor NM is turned off. Thus, the capacitor 44 starts to be charged, and the frequency voltage Vf will increase. As described above, the charge and discharge of the capacitor 44 are repeated to generate the oscillation clock OSCK.
Herein, the cycle period T of the oscillation clock OSCK will satisfy Equation (7) according to Equation (3) and Equation (6).T=2RfCf ln(n+1)  (7)
In the comparator circuits 22 and 24 of the oscillator 1, the driving speed differs depending on the amplitude of a bias current. For example, the driving speed increases as the bias current increases.
FIGS. 3A and 3B are timing diagrams illustrating a difference in the driving speed of the comparator circuit depending on the magnitude of the bias current. FIG. 3A is a timing diagram illustrating the driving speed of the comparator circuit when the bias current is small.
Referring to FIGS. 1 and 3A, the second comparator circuit 24 outputs the reset pulse Vr delayed by a first time ΔDT1, even if the second reference voltage V2 is equal to the frequency voltage Vf. Thus, the oscillation clock OSCK becomes a low-level state in response to the output reset pulse Vr. Also, the first comparator circuit 22 outputs the set pulse Vs delayed by the first time ΔDT1, even if the first reference voltage V1 is equal to the frequency voltage Vf. Thus, the oscillation clock OSCK becomes a high-level state in response to the output set pulse Vs.
FIG. 3B is a timing diagram illustrating the driving speed of the comparator circuit when the bias current is large.
Referring to FIGS. 1 and 3B, the second comparator circuit 24 outputs the reset pulse Vr delayed by a second time ΔDT2, even if the second reference voltage V2 is equal to the frequency voltage Vf. Herein, the second time ΔDT2 is shorter than the first time ΔDT1 illustrated in FIG. 3A.
The driving speeds of the comparator circuits 22 and 24 increase as the bias current increases. Thus, as the required frequency of the oscillation clock OSCK increases, the bias current must also increase to improve the operational characteristics. However, an increase in the bias current leads to an increase in the power consumption.